The present invention relates to a nonvolatile semiconductor memory component, particularly to its structure.
In the conventional nonvolatile memory cell, a dc voltage 12-15 V is applied to a control gate 6 and 6-8 V, enough to generate hot electrons in drain region, is applied to a drain 7 to inject electrons into a floating gate 5 during a program. So, cell becomes enhancement type as more hot electrons, having enough energy to surmount gate oxide barrier, store at the floating gate. Thus, a large dc current flows in cell array because a high voltage is applied to the control gate 6 and drain 7 during the program.
In addition, OV is applied to the control gate 6 and dc 12-18 V is also applied to the drain 7 to erase the cell array, thereby causing the injected electrons to tunnel through gate oxide toward the drain 7. Thus, floating gate oxide 2 degradation problem will be occurred as the number of program/erase cycles increase.